RTL coding gives agentic models a harder test

NVIDIA’s Nemotron 3 Ultra result is notable because RTL coding is not ordinary software generation. A useful hardware-design assistant must read specifications, modify existing modules, interpret simulator failures, reason about timing behavior, and correct code across repeated attempts. NVIDIA says Nemotron 3 Ultra averaged a 97.1% pass rate across nine categories of the CVDP benchmark while using 6,629 tokens per iteration.

“We tested Nemotron 3 Ultra on agentic chip design. The task is RTL coding: a model iteratively writes the code that defines a chip's logic, runs it through a simulator, reads the failures, and rewrites.”

The source tweet from NVIDIA AI compresses a longer developer blog into one concrete claim: agentic chip design should be measured as a generate-test-reflect loop, not as a single Verilog prompt. @NVIDIAAI usually posts developer-facing updates on models, inference infrastructure, and benchmarks, so this item fits its technical release pattern.

The evaluation used ACE-RTL, an agentic context evolution workflow with three cooperating parts. A generator writes or revises RTL. A reflector reads simulation feedback and identifies likely causes of failure. A coordinator decides which history and debugging context should guide the next attempt. This matters because real hardware engineers also iterate through compilers, simulators, lint tools, waveform inspection, and verification feedback rather than solving complex RTL tasks in one pass.

With the ACE-RTL pipeline held fixed, NVIDIA reports that Nemotron 3 Ultra reached 97.1% average pass rate across CVDP categories, compared with 95.2% for Kimi K2.6 and 92.1% for GLM 5.2. It also used fewer tokens: 6,629 per iteration versus 9,156 for GLM 5.2 and 22,579 for Kimi K2.6. That is roughly 28% below GLM 5.2 and 71% below Kimi K2.6, which is material for long-running design loops where each failed simulation can add more context.

NVIDIA describes Nemotron 3 Ultra as a 550B total-parameter, 55B active-parameter Hybrid Mamba-Attention Mixture-of-Experts model with a 1M-token context length. The blog also points to RTL-focused synthetic training data covering generation, editing, and debugging tasks. The next thing to watch is whether integrations with Cadence, Siemens, and Synopsys turn these benchmark gains into shorter verification cycles inside production EDA workflows.

#chip-design

Nemotron 3 Ultra Reaches 97.1% Pass Rate on Agentic RTL Tasks